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asynchronous communication - traducción al holandés
TRANSMISSION OF DATA WITHOUT THE USE OF AN EXTERNAL CLOCK SIGNAL
asynchronous communication
Asynchronische communicatie (uitzending van tekens geïdentificeerd door begin en beëindigende slagen)
Universal Asynchronous Receiver Transmitter
![Example of a UART frame. In this diagram, one [[byte]] is sent, consisting of a start bit, followed by eight data bits (D0-7), and two stop bit, for a 11-bit UART frame. The number of data and formatting bits, the presence or absence of a parity bit, the form of parity (even or odd) and the transmission speed must be pre-agreed by the communicating parties. The "stop bit" is actually a "stop period"; the stop period of the transmitter may be arbitrarily long. It cannot be shorter than a specified amount, usually 1 to 2 bit times. The receiver requires a shorter stop period than the transmitter. At the end of each data frame, the receiver stops briefly to wait for the next start bit. It is this difference which keeps the transmitter and receiver synchronized.
BCLK = Base Clock](https://commons.wikimedia.org/wiki/Special:FilePath/UART-signal.png?width=200 "Example of a UART frame. In this diagram, one [[byte]] is sent, consisting of a start bit, followed by eight data bits (D0-7), and two stop bit, for a 11-bit UART frame. The number of data and formatting bits, the presence or absence of a parity bit, the form of parity (even or odd) and the transmission speed must be pre-agreed by the communicating parties. The \"stop bit\" is actually a \"stop period\"; the stop period of the transmitter may be arbitrarily long. It cannot be shorter than a specified amount, usually 1 to 2 bit times. The receiver requires a shorter stop period than the transmitter. At the end of each data frame, the receiver stops briefly to wait for the next start bit. It is this difference which keeps the transmitter and receiver synchronized.
BCLK = Base Clock")
COMPUTER HARDWARE DEVICE
UART; Serial uart; UART overrun; Uart; Universal asynchronous receiver transmitter; Serial Communication Interface; 16450; Serial Communication Controller; Universal asynchronous receiver/transmitter; 16C450; 16450 UART; 16450 (UART); NS16450; PC16450C; Serial communication interface; Motorola 6850
universele asynchrone ontvanger/ zender, circuit die informatie omzet in gelijkstroomsignalen en gebruik maakt van seriële poorten, UART
non-verbal communication
![physical contact]].](https://commons.wikimedia.org/wiki/Special:FilePath/AModesMannersC.jpg?width=200 "physical contact]].")
![A [[high five]] is an example of communicative touch.](https://commons.wikimedia.org/wiki/Special:FilePath/High-five.jpg?width=200 "A [[high five]] is an example of communicative touch.")
![Symbol table for non-verbal communication with [[patient]]s](https://commons.wikimedia.org/wiki/Special:FilePath/PatientCommTbl.png?width=200 "Symbol table for non-verbal communication with [[patient]]s")
PROCESS OF COMMUNICATION THROUGH SENDING AND RECEIVING WORDLESS (MOSTLY VISUAL) CUES BETWEEN PEOPLE
Non-verbal; Non-verbal communication; Nonverbal; Nonverbal and Gestural Communication; Non verbal communication; Nonverbal intimacy; Nonverbal Intimacy; Nonverbal communication (NVC); Gestural communication; Nonverbal language; Artifactics; Nonverbal cues; Speech-independent gestures; Nonverbal Communication; User talk:HebinCMN2160/Nonverbal communication
niet-verbale communicatie (het doorgeven van informatie zonder gebruik van woorden)
Definición
asynchronous logic
<architecture> A data-driven circuit design technique where,
instead of the components sharing a common clock and
exchanging data on clock edges, data is passed on as soon as
it is available. This removes the need to distribute a common
clock signal throughout the circuit with acceptable {clock
skew}. It also helps to reduce power dissipation in CMOS
circuits because gates only switch when they are doing
useful work rather than on every clock edge.
There are many kinds of asynchronous logic. Data signals may
use either "dual rail encoding" or "data bundling". Each dual
rail encoded Boolean is implemented as two wires. This
allows the value and the timing information to be communicated
for each data bit. Bundled data has one wire for each data
bit and another for timing. Level sensitive circuits
typically represent a logic one by a high voltage and a logic
zero by a low voltage whereas transition signalling uses a
change in the signal level to convey information. A speed
independent design is tolerant to variations in gate speeds
but not to propagation delays in wires; a delay insensitive
circuit is tolerant to variations in wire delays as well.
The purest form of circuit is delay-insensitive and uses
dual-rail encoding with transition signalling. A transition
on one wire indicates the arrival of a zero, a transition on
the other the arrival of a one. The levels on the wires are
of no significance. Such an approach enables the design of
fully delay-insensitive circuits and automatic layout as the
delays introduced by the layout compiler can't affect the
functionality (only the performance). Level sensitive designs
can use simpler, stateless logic gates but require a "return
to zero" phase in each transition.
http://cs.man.ac.uk/amulet/async/.
(1995-01-18)
Wikipedia
Asynchronous communication
In telecommunications, asynchronous communication is transmission of data, generally without the use of an external clock signal, where data can be transmitted intermittently rather than in a steady stream. Any timing required to recover data from the communication symbols is encoded within the symbols.
The most significant aspect of asynchronous communications is that data is not transmitted at regular intervals, thus making possible variable bit rate, and that the transmitter and receiver clock generators do not have to be exactly synchronized all the time. In asynchronous transmission, data is sent one byte at a time and each byte is preceded by start and stop bits.
